The continuing push to produce faster semiconductor devices with lower power consumption has resulted in the miniaturization of semiconductor devices. With shrinking process geometries, comes a number of new design issues. For instance, reducing gate oxide thickness and channel width are conducive to the low voltage and faster operation of a field effect transistor (FET). Such smaller designed FETs, however, are more susceptible to leakage currents, or punch through, when the transistor is off.
One approach to reduce the leakage current is to form shallow source and drain regions immediately next to the gate. Such shallow junctions or lightly doped drain (LDD) regions, are near the substrate's surface and the channel region, acting as extensions to the more heavily doped source and drain region. It is desirable for a shallow junction to have a well-defined boundary, as exemplified by an abrupt decrease in dopant concentration, to support low-voltage operation of the FET and to define the width of the channel region. The efficient fabrication of transistors having shallow junctions with a well-defined boundary has been problematic, however.
Shallow junctions typically are formed by ion implantation of dopant species, followed by rapid or spike thermal annealing, to electrically activate the dopant. To establish n-type doped shallow junctions in a negative channel metal oxide semiconductor (NMOS) transistor, typical dopants include arsenic (As+), or at low implantation energies, arsenic dimer (As2+). To establish p-type doped shallow junctions in a positive channel metal oxide semiconductor (PMOS) transistor, a typical dopant is boron (B+). Low mass dopants, such as boron, however, are subject to undesired enhanced diffusion into the implantation-caused damaged lattice structure of silicon substrates during thermal annealing, known as transient enhanced diffusion (TED). TED is undesirable because it decreases the abruptness of the change in dopant concentration from the shallow junction to a p-well or n-well that the shallow junction is formed in. This, in turn, deters the formation of shallow junctions having suitably shallow depths (e.g., less than about 100 nm). TED can also cause dopants, such as boron, to diffuse in the channel region, thereby causing an unfavorable change in the doping concentration in the channel, an increase in electron trapping, a decrease in low-field hole mobility, and a degraded current drive. Although numerous procedures have been proposed to mitigate TED, each is problematic.
One such procedure involves forming a thermal oxide screen over the silicon substrate, and performing the boron implant through the screen. Forming a thermal oxide, such as silicon dioxide, however, significantly increases the thermal budget for transistor fabrication. Another proposal to mitigate TED is to perform low energy (e.g., ˜5 keV or less) implants using higher mass dopant species, such as boron difluoride (BF2). Many ion implantation tools, however, are not designed to perform low energy implantation. Accordingly, there are increased problems in controlling the uniformity of implantation of the dopant. Yet another way to reduce TED is to implant a heavier dopant, such as phosphorus, into the tips of the LDD nearest the channel so as to block the diffusion of boron into the channel region. Phosphorus, however, is also subject to TED, although to a lesser extent than boron.
Still another way to mitigate TED is to perform an implantation step of implant species that are electrically inactive elements, such as germanium. However, the high doses of germanium needed to amorphize the surface regions of the silicon substrate also damages regions deep within the silicon substrate, creating channels through which boron can diffuse during the thermal anneal. This undesirably results in a shallow junction having a diffuse boundary. Alternatively, low doses of antimony, an electrically active heavy atom (atomic mass unit (AMU) equal to about 122) can be used to localize the damage to surface regions of the substrate.
There are a number of unfavorable aspects in using antimony, however. For example, a gaseous source of antimony is not available. Because a solid source of antimony must be used, it is more difficult to control the flow of antimony into the ion implantation tool. This decreases the uniformity of antimony deposited. Moreover, antimony must be heated to a high temperature (˜500° C.) to vaporize the material. Therefore, longer periods are required between implantation steps of different species using the implantation tool, resulting in a decrease in the rate of production of transistors. In addition, there is also an increase risk of implant species cross-contamination of the implantation tool, which may necessitate the dedication of an implant tool solely to antimony implantation, thereby increasing the total cost of transistor production. Furthermore, the lifetime of source and electrodes in the implantation tool used to implant antimony is shortened, due the increased coating and arcing caused by a tendency to over vaporize because of the difficulties in controlling the flow of antimony into the ion implantation tool.
Accordingly, what is needed in the art is an improved method of manufacturing shallow junctions in transistors that avoid the above-mentioned limitations.